This invention relates generally to power-up reset circuits and more particularly, it relates to an improved power-on reset circuit which includes means for maintaining a reset signal in an active low state during the initial power-up until after the power supply voltage exceeds a predetermined level and means for automatically turning off the reset circuit after the predetermined level has been reached.
In a variety of digital integrated circuit components such as flip-flops, latches, counters, and memory state registers or the like, the outputs thereof can have two or more stable states. It is often desirable to initialize or reset these types of components to a particular known logic state prior to their normal operation every time when power is first applied. As is generally well-known, this initialization process is commonly achieved by a reset signal which is applied for a brief period of time after the power is turned on to reset or initialize the outputs of the digital integrated circuit components. Thus, proper initialization insures the operating state of the various logic elements in the digital components and also simplifies test procedures to be performed thereon.
It is generally desirable to minimize the time during which the reset signal is active to the shortest time required for initializing the various components in order that they become functional as quickly as possible. It is also desirable to have the power-up rest circuit be turned off after the duration of the reset signal so as to conserve power consumption. In order to reduce space, it would be expedient to have the power-up reset circuit formed as a part of the same monolithic semiconductor integrated circuit chip containing the logic and/or memory circuits.